Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance

SAN JOSE, Calif., September 01, 2026--Cadence (Nasdaq: CDNS) today announced that its PHY and controller IP for the PCI Express® (PCIe®) 6.0 specification, implemented in the TSMC N3 process, achieved first-pass success at the recent PCI-SIG® compliance workshop held in late July. The workshop marked the industry’s first official event for PCIe 6.0 specification compliance testing, with Cadence’s x8 subsystem solution tested at the full PCIe 6.0 specification speed of 64 GT/s.